Advanced VLSI-Design (WS 2020/21)

Important links

Room reservation plans for PC pools with required software:
WM1216 and WM1218

References to other portals for this module:
Advanced VLSI in StudIP and in LSF

 

Older VLSI projects

Course information

Schedule: The project starts on November 4th, 2020 and ends on January 27th, 2021 (WS 2020/21).
Title: Advanced VLSI Design, Module Nr. 24151

IMPORTANT: Meetings will take place as scheduled in the Timetable via online conferencing tool in StudIP. Please subscribe to the StudIP module to receive short-term information about the meetings.

Good and very good grades depend on various aspects like attending ALL meetings, independent and regular work on the given tasks, proper and methodical documentation as well as qualified presentations of achieved results, conclusions and optimizations! Please upload all your paper work (docs, hints & advices, slides) and slides before the deadlines. Your presentation slides must be sent 1 DAY BEFORE the scheduled meeting for the presentation! Your work will be added to this website.

As the work is primarily performed in our laboratories, consider the associated general rules of regulation.

Timetable

Date Milestone Description
November
4th 		Kick-Off Meeting:
start phase 1 		Introduction
TBA VHDL-Recap Recapitulation of VHDL and VHDL project setup
November
18th 		Intermediate meeting:
Start phase 2 		Presentation of first results for FPGA and definition of new target: FPGA design shall run at least on 100 MHz clock speed
December
2th 		Intermediate meeting:
Start phase 3 		Presentation of backannotated results for FPGA and start of last FPGA optimization phase to achive the best FPGA design in the competition
December
16th 		Intermediate meeting:
Start phase 4 		Presentation of final FPGA design and start of 65nm ASIC phase: Synthesis with Synopsys tools
January
13th 		Intermediate meeting:
Start phase 5 		Presentation of Synopsis synthesis of 65nm ASIC and start of CADENCE chip layout
January
27th 		Final meeting Presentation of Cadence chip layout and final metrics for competition and awards

Presentation

  • Each presenter has 5 minutes. The last minute will be indicated. Be aware of your time (5 min), no extra time will be given. Thus, prepare and test your talk at home.
  • Accepted file formats are solely ppt and pdf (to avoid conflicts with faulty display do not use latest versions or features that might not be widely supported)
  • We want to know:
    • Which problems and room for optimization did you observe in your last design/approach? (with the design, not with the tools)
    • How did you try to tackle the problem(s), what did you expect before starting to investigate (i.e. in theory)?
    • Do your results prove your approach? Why or why not?
  • Please do not just copy and paste blurry and skewed images from the literature into your slides. We appreciate self-made diagrams, pictures and sketches. It simply looks better and makes the understanding easier!
  • Presentations can be given in GERMAN. However slides have to be prepared in ENGLISH.
  • Template for your presentation slides: slides

Phase 1 (2 weeks)

  • Tutors:
    • M.Sc. Franz Plocksties
    • M.Sc. Jakob Heller
  • Tasks:
    • Get familiar with filter theory and its operation
    • Use the Xilinx FPGA synthesis tools and the ModelSim simulation environment
    • Direct implementation of the FIR filter (do not use + and *-operators)
    • The target Hardware you have to choose in the Xilinx Vivado Project is a Zedboard.
    • Template and important hints for the presentation of achieved results: see below (can be used, no must)
    • The constraints-file (.xdc) is required to define a targeted operating frequency for the synthesis tools
    • Target: Your first working FIR filter design
  • Required files can be found in StudIP, see link above

Phase 2 (2 weeks)

  • Tutors:
    • M.Sc. Franz Plocksties
    • M.Sc. Jakob Heller
  • Tasks:
    • Architectural / component optimization (adders, multipliers, CSD, pipelining, parallelization, term sharing, ...)
    • Results for the next presentation have to include values for the synthesized and backannotated design
    • The constraints-file (.xdc) may be used to define further directives (e.g. for pin positions or timing constraints for various signals)
    • Target: A better design, in terms of the metric, running at 100MHz

Phase 3 (2 weeks)

  • Tutors:
    • M.Sc. Franz Plocksties
    • M.Sc. Jakob Heller
  • Tasks:
    • Architectural / component optimization (adders, multipliers, CSD, pipelining, parallelization, term sharing, ...)
    • Test your design on a ZedBoard evaluation Platform
    • Present the quality of your filter to your tutors before next meeting

Phase 4 (2 weeks)

  • Tutors:
    • M.Sc. Franz Plocksties
  • Tasks:
    • Mapping on ST65 technology
    • Further design improvements using the synthesis scripts and tools (architectural changes are welcome but we want to primarily see an adaptation of your design due to the ASIC technology instead of the FPGA and we expect you to purposefully enhance the synthesis scripts for your design requirements)
    • Remark: For a correct power simulation, your design hierarchy must be flat (ungroup)!
    • Target: A working and optimized ST65 netlist

Phase 5 (2 weeks)

  • Tutors:
    • M.Sc. Hannes Raddatz
  • Tasks:
    • Layout for ST65 technology
    • However, investigations and optimizations in all phases are welcome (this is the last phase for the design contest)
    • Usage of 'Cadence Innovus' and 'Synopsys Design Vision' to achieve backannotated results of a chip layout
    • Remark: Your final netlist may not include slashes and backslashes
    • For presentation: Include a picture of your chip layout together with the results (f, Pdyn, Pleak, Acore, chip utilization, metric)
    • Target: Complete ST65 layout and backannotated results